Recently, two research achievements from Professor ZHANG Jiliang's team at the School of Integrated Circuit Science and Engineering (School of Industry-Education Integration), Nanjing University of Posts and Telecommunications (NJUPT), have been accepted by ISCA in the field of chip architecture and DAC in the field of integrated circuit design automation, respectively. With these acceptances, NJUPT's integrated circuit discipline has now achieved full coverage across top-tier conferences: IEDM in devices, ISSCC in design, ISCA in architecture, and DAC in EDA.
ISCA (International Symposium on Computer Architecture) is the longest-running and most influential top-tier conference in the field of computer architecture. Jointly sponsored by ACM SIGARCH and IEEE TCCA, it is widely regarded as the Oscars of the architecture world. Many innovative applications in chip architecture have originated from research findings presented in this conference's papers. DAC (Design Automation Conference) is the premier international academic conference in electronic design automation (EDA) and chip systems, covering such hot topics as EDA tool development, AI/ML chip design, and hardware security. It is the only EDA conference classified as Category A by the China Computer Federation (CCF).
The paper accepted directly for presentation at the 53rd ISCA 2026 is titled L-PCN: A Point Cloud Accelerator Exploiting Spatial Locality through Octree-based Islandization. Its first author is Dr. GAO Yiming from NJUPT's School of Integrated Circuit Science and Engineering (School of Industry-Education Integration), with Professor ZHANG Jiliang as the corresponding author. Collaborators include Professor YIN Jieming from NJUPT's School of Computer Science, School of Software, and School of Cyberspace Security, and Professor Herman Lam from the University of Florida, among others. This marks NJUPT's first time publishing research at a top-tier architecture conference, and it is also the first ISCA paper published with a Jiangsu provincial university as the first affiliation.
Currently, most point cloud accelerators focus on developing dedicated feature map aggregation units and use NPU for feature computation. However, due to numerous duplicate points across feature maps in point cloud neural networks, the NPU workloads in such accelerators incur substantial redundant memory access and computation. Drawing inspiration from cross-feature-map data reuse in graph convolutional network (GCN) accelerator design, the research team proposes a hardware-software co-design approach (L-PCN) to exploit the spatial locality of point cloud networks. At the software level, an islandization step is introduced, which can reduce memory accesses by up to 93.8% and computations by up to 80.6% for point cloud models. At the hardware level, an islandization unit is designed and naturally integrated into existing point cloud accelerators, delivering an additional speedup of up to 3.2×. This work outperforms existing methods for optimizing point cloud feature computation in terms of both speed and accuracy preservation.
Islandization Unit Functional Example: After the Feature Map Aggregation Unit, Convolution Result Reuse Helps the Feature Computation Unit Avoid Redundant Memory Accesses and Computations
The paper accepted by the 63rd DAC 2026 is titled Leveraging AI-Inspired Hardware Architecture to Enhance LPN Acceleration in Post-Quantum Cryptography. Its first author is Associate Professor GAO Yingxue from NJUPT's School of Integrated Circuit Science and Engineering (School of Industry-Education Integration), with Professor ZHANG Jiliang as the corresponding author. In post-quantum cryptography (PQC), the Learning Parity with Noise (LPN) problem, known for its simple structure and strong security, is regarded as an ideal primitive for building efficient cryptosystems. However, existing LPN accelerators mostly focus on local computation optimization while neglecting overall execution flow and data transfer bottlenecks, leading to limited hardware utilization and system throughput. Inspired by AI accelerator architectures, the research team proposes an FPGA-oriented LPN hardware acceleration architecture for the first time, named LHPA. LHPA employs heterogeneous computing engines, a hierarchical XOR reduction tree, and a streaming execution mechanism to holistically optimize multi-stage computation and data transfer for LPN. To address the multi-transfer, single-bit data characteristics in LPN, a coalesced access handler and a phase-level scheduling strategy are designed, boosting off-chip transfer efficiency by 51.16%, significantly alleviating the memory access bottleneck and enhancing architectural adaptability. Experimental results show that on a Zynq UltraScale+ FPGA, LHPA achieves a 52.80× performance improvement over the state-of-the-art LPN accelerator (PIM-LPN), and improvements ranging from 36.69× to 247.35× compared with mainstream PQC accelerators (BIKE, HQC, Kyber). Its average hardware utilization reaches 90.71%, and memory access efficiency improves by up to 47.25%. LHPA is the first AI-inspired architecture to achieve efficient, configurable, and high-throughput LPN acceleration on an FPGA, charting a new path for post-quantum cryptography hardware design.
Overall Architecture of LHPA
NJUPT has been building a comprehensive five-in-one information discipline system encompassing information materials, information devices, information systems, information networks, and information applications. Focusing on bottleneck technological challenges in the integrated circuit field, the university is deepening industry-education integration, strengthening organized research, and striving for original and groundbreaking breakthroughs in frontier areas, thereby contributing NJUPT's strength to the independent and controllable development of the nation's IC industry and the cultivation of top-tier innovative talent.
(Authors: Gao Yiming, Gao Yingxue, Wang Haihua; Preliminary Review: Gao Xiang, Li Bingxiang; Editor: Wang Cunhong; Final Review: Zhang Feng)
